This invention is directed generally to improvements in the fabrication of semiconductor devices. It is particularly directed to improved processing techniques for fabricating MOS (metal oxide semiconductor) transistors in a large scale integrated circuit.
An MOS transistor generally includes source/drain regions in a substrate, and a gate electrode formed above the substrate between the source/drain regions and separated from the substrate by a relatively thin dielectric. The relative alignment of the gate with its source/drain regions is an important factor which influences the performance of the transistor.
Conventional fabrication techniques usually cause edges of the source/drain regions to be initially substantially vertically aligned with the edges of their gate. In subsequent heat treatment steps, however, the source/drain regions diffuse laterally. This results in the edges of the gate overlapping the source/drain regions. Consequently, undesired gate-drain overlap and Miller capacitances are created, and the operating speed of the transistor is reduced.
In an attempt to avoid the foregoing problem, it has been proposed to establish a photoresist or dielectric layer on top of the gate such that the gate can be undercut to provide a photoresist or dielectric area which overhangs the edges of the gate. This overhang defines a source/drain implant area which laterally separates the source/drain implants from the nearby edges of the gate. However, the amount of the undercut is difficult to control. Consequently, alignment between the gate and the source/drain regions fluctuates substantially.
A related problem concerns the contacts for the source/drain regions. Except by imposing tight tolerances on the manner in which the contacts are patterned, it has been difficult to provide well aligned source/drain contacts which are well isolated from the gate electrode.
For the foregoing reasons, conventional fabrication techniques are not perfectly satisfactory for the construction of high speed, very large scale integrated circuitry, particularly where high packing density is a paramount concern.